1. Field of the Invention
The present invention relates to a teletext data separation apparatus for separating superimposed teletext data from a composite video signal decoded by a receiver of a television broadcast.
2. Description of Related Art
Today, the television broadcasts have spread widely throughout the world, and individual homes can enjoy video information transmitted by terrestrial broadcasting, cable broadcasting or satellite broadcasting by receiving it by TV receivers. In addition, teletext services become available which provide text information superimposed on a composite video signal of ordinary television broadcasts. The teletext services, which offer text information as well as graphics on the TV screens, provide various services according to the difference of transmission standards. For example, Japan has propagated teletext (ADAMS), the U.S. has propagated CCD (Closed Caption Decoder) and Europe and Southeast Asia have propagated TELETEXT. In any of these teletext services, a broadcasting station superimposes the teletext information on the vertical blanking period of the composite video signal, and transmits it in conjunction with the video information. Then, a receiver separates the teletext data from the received composite video signal, decodes the data and displays the decoded data on a TV screen.
Next, TELETEXT that has come into wide use in Europe will be described. FIG. 7 illustrates a state of the signal in the vertical blanking period, on which the teletext data is superimposed. The teletext data is superimposed on the sixth to 22th lines and 318th to 335th lines in the vertical blanking period. FIG. 8 illustrates some types of teletext data having a packet structure. The initial two bytes in the data region are composed of a Hamming code and include the packet number and magazine number. The Hamming code consists of eight bits, four bits of which constitute data and another four bits correction data. Thus, it can carry out 1-bit error correction and 2-bit error detection. The two items of information, the packet and magazine, are provided for specifying the use of the information of the following data, and for processing the text information or control code. In addition, the Hamming code, which is used for error correction of the data, reduces errors occurring during the transmission. The packet No. 0 is used as a header, Nos. 1–25 are used as 40×25 row display data, Nos. 26–28 are used as extended display data and navigation function data, No. 29 is used as magazine-specific information, and No. 30 is used as data for distinguishing time, recording information and the like used frequently in a VTR.
FIG. 9 is a block diagram showing a configuration of a conventional teletext data separation apparatus. In FIG. 9, the reference numeral 120 designates a RAM for storing separated teletext data (called “TEXT data” from now on); and 150 designates an A/D converter for sampling a TEXT signal superimposed on a composite video signal and for quantizing it to digital data. The reference numeral 130 designates a digital operation circuit for obtaining TEXT data from the digital data output from the A/D converter 150; and 160 designates a sync separation circuit for separating from an input video signal the vertical sync signal (called “Vsync” from now on) and a horizontal sync signal (called “Hsync” from now on). The reference numeral 170 designates a PLL (Phase Locked Loop) circuit for generating an operational clock signal of the teletext data separation apparatus; and 200 designates a slice level generating circuit for generating a slice level using a calculation result of the digital operation circuit 130. The reference numeral 250 designates a comparator for comparing the generated slice level with the TEXT data generated by the digital operation circuit 130 to restore the teletext data at the normal (transmission) mode. The reference numeral 110 designates a control register for controlling the ON/OFF operation of a slice timing control circuit 140 (FIG. 14) in the slice level generating circuit 200. The slice timing control circuit 140 is connected via a bus 108 to a CPU (Central Processing Unit) for carrying out various types of processing in the receiver according to software, and is supplied with control signals for controlling writing and reading.
Next, the basic operation of the conventional teletext data separation apparatus will be described.
The composite video signal, on which the TEXT data as shown in FIG. 10 is superimposed, is input to the A/D converter 150 and sync separation circuit 160. The sync separation circuit 160 separates the horizontal sync signal Hsync and the vertical sync signal Vsync from the composite video signal, and outputs them after shaping. The PLL circuit 170 operates in response to the generated Hsync used as a reference clock signal in such a manner that it locks to the Hsync, thereby generating the operational clock signal (called “VCO clock” from now on) of the teletext data separation apparatus. The slice timing control circuit 140 (FIG. 14) controls the following slicing operation in response to the generated Vsync, Hsync and VCO clock.
The A/D converter 150 samples the TEXT signal superimposed on the incoming composite video signal. FIG. 11 illustrates a example of the sampling within a single bit width of the data. The sampling timings are designated by t1, t2, t3 and t4, and the sampled values at the sampling timings are designated by X1, X2, X3 and X4.
FIG. 12 is a schematic diagram illustrating the sampling and operation process of the digital operation circuit 130. In FIG. 12, reference numerals 151–159 each designate a latch circuit, 132 and 134 each designate an adder, and the reference numeral 133 designates an integrator.
Reference symbols N−4–N+4 each designate a sampling point. The sampling points N−4–N−1 are converted to the digital data in each bit width at the timings t01, t02, t03 and t04. The following bit is sampled at the timings t05, t06, t07 and t08. Thus, the sampling is carried out continuously.
Subsequently, the results of the sampling and A/D conversion are stored into the latch circuits 151–159 sequentially in FIG. 12. For example, when the sampling point N−4 is stored in the latch circuit 159, the sampling point N−3 is stored into the latch circuit 158, N−2 into the latch circuit 157, N−1 into the latch circuit 156, N into the latch circuit 155, N+1 into the latch circuit 154, N+2 into the latch circuit 153, N+3 into the latch circuit 152, and N+4 into the latch circuit 151.
These sampled values are latched so that the value of the sampling point N is obtained not from the value Xn latched in the latch circuit 155, but from the value corrected using its neighboring sampled values latched. The value Xn takes “0” or “1” finally.
The conventional digital operation circuit 130 uses the adders 132 and 134 and the integrator 133 to obtain the corrected value F(Xn) of the latched value Xn according to the following equation.
                              F          ⁡                      (                          X              n                        )                          =                              aX            n                    +                      bX                          n              -              4                                +                      cX                          n              +              4                                +          d                                        =                              aX            n                    -                      X                          n              -              4                                -                      X                          n              +              4                                          where, b=c=−1 and d=0. The constant a is set in a part of the control register 110.
The comparator 250 compares the corrected value F(Xn) with a predetermined slice level so that the value Xn takes a value “0” or “1”. A value corresponding to the operation corrected result F(Xn) is supplied to a first adder 210 (FIG. 14) of the slice level generating circuit 200.
FIG. 13 is a timing chart illustrating waveforms of the actual operation of the teletext data separation apparatus. The waveform (b) is a result of the separation when the video signal (a) is input. It is converted into binary data “0” and “1” bit by bit in response to the sampling clock (c), and the binary data is stored into the RAM 120 operating as a buffer. A slice level A0 is generated by averaging the 16 sampled values a1–a16 in the clock run-in portion as illustrated in FIG. 10. It is also possible to add an offset C0 according to the register value of the control register 110.A0={(a1+a2+a3+ . . . +a15+a16)+C0}/16
FIG. 14 is a block diagram showing a configuration of the conventional teletext data separation apparatus, in which the slice level generating circuit 200 of FIG. 9 is shown in more detail. In FIG. 14, the reference numeral 140 designates a slice timing control circuit for controlling the timing of the entire separating operation of the teletext data separation apparatus. The reference numeral 210 designates a first adder, 220 designates a divider, 230 designates a second adder and 240 designates an offset register.
The conventional apparatus uses 16 sampling points for generating the slice level. In this case, the calculation result F(a) by the first adder 210 is given by the following expression.F(a)=a1+a2+ . . . +a15+a16where ai (i=1–16) designate the sampling points. The operation of the divider 220 is given by the following expression.G(x)=x/16=F(a)/16where x is the sum output from the first adder 210.
Here, the offset register 240 is used for setting the offset value to the slice level. The offset value of the offset register 240 is set using software, a procedure of which is illustrated in FIG. 15. In FIG. 15, the data about the slice level is input and stored (step ST51). Then the software makes a decision as to whether the number of the data equals a specified sampling number A or not (step ST52). If the sampling number reaches the specified number A, the software calculates the average value Y (step ST53). Subsequently, the software makes a decision as to whether the average value Y is greater than the target value B of the slice level (step ST54). If it is greater, the software subtracts the fine adjustment value C from the offset value (step ST55), whereas it is smaller, the software adds the fine adjustment value C, thereby completing the processing (step ST56). Then, the software returns to the storing operation of the next data about the slice level (from step ST57 to ST51).
With the foregoing configuration, the conventional teletext data separation apparatus has the following problems.
The number of the sampling points for generating the slice level is fixed at 16 points. Although an increasing number of the sampling points will be able to improve the slice characteristic, it will increase the current consumption or spurious emission of the processing circuit. Considering these merit and demerit, the number of the specified points is determined at 16 points. However, generating the slice level from the 16-point sampled data for separating the teletext data has the following problems. First, it cannot achieve an appropriate level when the reception is made under a bad condition such as a weak electric field or ghost.
Second, although the conventional circuit generates the slice level during the initial two clock pulses of the clock run-in signal of FIG. 10, it has a problem in that it cannot generate a satisfactory slice level in a bad condition. This is because the number of clock pulses of the clock run-in signal can vary from that of the normal case, or it can become an irregular signal with insufficient peak value or waveform.
Third, it has a problem in that the volume of software grows heavier with the processing speed because of the following reason. To set the offset value of the offset register 240, the state of the irregular signal must be fed back quickly. Although the conventional circuit carries out the feedback processing by software, the processing time of the feedback depends on the clock frequency of a microcomputer. Accordingly, the volume of the software grows heavier with the speed of the feedback processing required.
Moreover, the conventional circuit as shown in FIG. 14 uses the sampled data output from the A/D converter 150 to generate the slice level. However, when the microcomputer operates, its noise is usually superimposed on its power, which offers a problem of having an adverse effect on the power supply of the A/D converter 150, thereby degrading its conversion accuracy.